Efficient implementation of packet pre-filtering for scalable analysis of IP traffic on high-speed lines

In this paper an efficient FPGA implementation of a packet pre-filtering algorithm based on Bloom filter is presented. In high speed link the traffic classification involves a very large amount of data per each packet processed. Both header and payload should be analyzed. This leads to use hardware with high computational power and very expensive, in order to support requirement of real-time classification. Our system, reducing the data flow sent to the classifier allows a realtime classification with reduced hardware resources.