DocumentCode
2119465
Title
Design and Implementation of LDPC Codec for Aircraft Control and Simulation
Author
Qi, Jinqing ; Zhang, Jingbin ; Ma, Xiaohong ; Sun, Yi ; Yu, Yan
Author_Institution
Sch. of Inf. & Commun. Eng., Dalian Univ. of Technol., Dalian, China
fYear
2010
fDate
24-26 Dec. 2010
Firstpage
219
Lastpage
223
Abstract
The system is based on the platform of Altera DE2 SOPC and RS232 interface using a wireless channel environment. NIOS_II processor and FPGA hardware co-design methodology is adopted. The soft-core processor asks for a request to send codec allocation and other operations and FPGA is responsible for the major hardware codec. The LDPC codec system can achieve a two-way communication with flexible configuration, which is particularly suitable for satellite communications.
Keywords
aerospace simulation; aircraft communication; aircraft control; codecs; field programmable gate arrays; parity check codes; wireless channels; FPGA hardware codesign methodology; LDPC codec; NIOS II processor; aircraft control; aircraft simulation; satellite communications; soft-core processor; wireless channel environment; Codecs; Decoding; Encoding; Field programmable gate arrays; Parity check codes; Random access memory; Wireless communication; FPGA; LDPC; SOPC; codec;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Science and Engineering (ISISE), 2010 International Symposium on
Conference_Location
Shanghai
ISSN
2160-1283
Print_ISBN
978-1-61284-428-2
Type
conf
DOI
10.1109/ISISE.2010.31
Filename
5945088
Link To Document