New Tool and New Process for Ultra High Performance for Metal/High-K Gate Dielectric Stack for Sub-45 nm CMOS Manufacturing

Off stage power dissipation and profitability are posing fundamental and practical challenges to the scaling of Si CMOS to its limit. With escalating developmental cost, off state leakage current related power dominates the CMOS heat dissipation problem making the necessity of reducing the gate leakage current density to zero, so that the designer will get relief to focus on other imposing challenges. To continue to make big gains, as we scale down from 45 nm it is important to reduce the tool cost and turn to high-k materials. In this paper we report the results of a new process and tool to deposit metal/high-k gate dielectric stack. Hafnium oxide dielectric of 0.39 nm EOT is deposited using monolayer photoassisted deposition process on a home-built system. Our process has also reliably demonstrated the success achieved with low process induced variation of the system and this is the driving factor to convincingly make this an attractive alternate choice to existing tools. The leakage current density value reported in this paper represents the lowest value reported by anyone in the open literature. This is a major breakthrough and will have major impact on the silicon IC manufacturing.