High speed routing in a parallel processing environment: a simulation study

Author

Dowd, P.W. ; Carrato, M.

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

fYear

1991

fDate

1-5 Apr 1991

Firstpage

60

Lastpage

72

Abstract

This paper examines techniques to achieve high speed routing in a distributed memory parallel computer environment. This paper develops a model to analyze the intra-node routing latency, and demonstrates that it may be the dominant factor of the overall system performance. This paper introduces three approaches, with varying levels of relative complexity, to improve intra-node routing capability. A simulation study has been developed to compare the behavior of each technique with three different topologies. The approach presented in this paper applies the advantages of dynamic interconnection networks to the problem of static interconnection network routing

Keywords

digital simulation; multiprocessor interconnection networks; parallel processing; distributed memory; dynamic interconnection networks; high speed routing; intra-node routing latency; model; parallel processing environment; simulation; static interconnection network routing; Computational modeling; Concurrent computing; Delay; Distributed computing; Multiprocessor interconnection networks; Network topology; Parallel processing; Performance analysis; Routing; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation Symposium, 1991., Proceedings of the 24th Annual

Conference_Location

New Orleans, LA

Print_ISBN

0-8186-2169-9

Type

conf

DOI

10.1109/SIMSYM.1991.151486

Filename

151486