DocumentCode
2120564
Title
32nm Node USJ Implant & Annealing Options
Author
Borland, John O.
Author_Institution
J.O.B. Technol., Aiea
fYear
2007
fDate
2-5 Oct. 2007
Firstpage
181
Lastpage
189
Abstract
For the 32 nm node, using msec only dopant activation techniques reveal the potential for serious device variation caused by both single wafer high current implanter design and msec annealing micro-uniformity variation effects. New non-contact metrology techniques with <1mm detection resolution such as RsL (electrical Rs and leakage) and TW (thermal wave dose and damage detection) are required for process optimization to reduce these effects. Also, molecular dopant species (B18H22, P2 & As2) and high mass dopants (Sb) for n & p type SDE and HALO implantation are shown to give highest quality junctions and enhanced dopant activation with msec and SPE diffusion-less annealing techniques. To minimize strain-Si relaxation and high-k/metal gate degradation process integration trade-offs are required.
Keywords
annealing; antimony; arsenic; boron compounds; elemental semiconductors; ion implantation; phosphorus; silicon; stress relaxation; HALO implantation; Jk:As2; Jk:B18H22; Jk:P2; Jk:Sb; SDE implantation; SPE diffusion-less annealing techniques; Si; Si - Interface; USJ implant; dopant activation techniques; high-k-metal gate degradation process; mass dopants; molecular dopant; msec annealing techniques; non-contact metrology techniques; optimization; single wafer high current implanter design; strain-relaxation; Annealing; Capacitive sensors; Degradation; High K dielectric materials; High-K gate dielectrics; Implants; Lamps; Leak detection; Metrology; Temperature dependence;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Thermal Processing of Semiconductors, 2007. RTP 2007. 15th International Conference on
Conference_Location
Catania, Sicily
Print_ISBN
978-1-4244-1228-0
Electronic_ISBN
978-1-4244-1228-0
Type
conf
DOI
10.1109/RTP.2007.4383840
Filename
4383840
Link To Document