• DocumentCode
    2120571
  • Title

    Capacitance Calculation Of VLSI Multilevel Wiring Structures

  • Author

    Bauer ; Stiftinger, M. ; Selberherr, S.

  • Author_Institution
    Technical University of Vienna
  • fYear
    1993
  • fDate
    14-15 May 1993
  • Firstpage
    142
  • Lastpage
    143
  • Keywords
    Boundary conditions; Conducting materials; Conductors; Integrated circuit interconnections; Maxwell equations; Microelectronics; Parasitic capacitance; Very large scale integration; Visualization; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Process and Device Modeling, 1993. (1993 VPAD) 1993 International Workshop on
  • Print_ISBN
    0-7803-1338-0
  • Type

    conf

  • DOI
    10.1109/VPAD.1993.724760
  • Filename
    724760
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2120571