Title :
A low power data holding circuit with an intermittent power supply scheme for sub-1V MT-CMOS LSIs
Author :
Akamatsu, Hiroki ; Iwata, T. ; Yamamoto, H. ; Hirata, Takaomi ; Yamauchi, H. ; Kotani, Hiroaki ; Matsuzawa, A.
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
Abstract :
The data holding circuits which use an Intermittent Power Supply (IPS) scheme are proposed for sub-1V Multiple Threshold (MT) CMOS technology. This scheme can use low V/sub T/ transistors without any increase of leakage currents. As a result, no extra data holding circuit and no degradation of operating speed will be achieved. An experimental latch circuit has been fabricated in 0.35 /spl mu/m MT-CMOS technology and 30% smaller area, 10% shorter delay time, and 10% lower active power consumption compared with a conventional MT-CMOS circuit are realized. Furthermore this IPS scheme makes it possible to reduce the standby current of the SRAM to 0.4% compared with a conventional one at 100 MHz operation.
Keywords :
CMOS logic circuits; delays; flip-flops; large scale integration; leakage currents; 0.35 micron; MT-CMOS LSI; active power consumption; area; data holding circuit; delay time; intermittent power supply scheme; latch circuit; leakage currents; multiple threshold CMOS technology; standby current; CMOS technology; Circuits; Degradation; Delay effects; Energy consumption; Latches; Leakage current; Power supplies; Random access memory;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507697
