High-Activation Laser Anneal Process for the 45nm CMOS Technology Platform

This paper presents the integration of a sub-melt laser annealing technique in a 45 nm CMOS technology platform. To enhance the activation of transistors gates and source/drain junctions, ms anneal as dynamic surface anneal (DSA) is added to conventional low temperature spike process. The aim of this new integration scheme is to significantly increase the solubility limit of the dopants without appreciable diffusion. To prevent severe surface emissivity dependence of the process, a sacrificial absorbing layer is deposited prior to the annealing. The DSA laser technique has been developed with a key focus on process simplicity and manufacturability: an excellent within-wafer microscopic uniformity is reported, with no impact of the process on the wafer stress or defectivity level. Competitive drive currents are demonstrated with NMOS (PMOS) performance boost as large as 10% (5%) with respect to conventional rapid thermal anneal (RTA), without degradation of the short channel control or junction leakage. The effect of laser annealing on the transistor reliability is also carefully examined. Within a wide process window temperature (1000-1400degC), the gate oxide integrity remains unchanged. The deposition of the PEC VD absorbing film is also reported to be plasma-damage free.