DocumentCode
2121066
Title
Self resetting logic register and incrementer
Author
Haring, R.A. ; Milshtein, M.S. ; Chappell, T.I. ; Dhong, Sang H. ; Chappell, B.A.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1996
fDate
13-15 June 1996
Firstpage
18
Lastpage
19
Abstract
Register circuitry is described which is suitable for use with Self Resetting CMOS (SRCMOS) logic. It is level sensitive scan design (LSSD) compatible and complies with and implements the SRCMOS test modes. The register has been coupled to a novel high performance self resetting incrementer, which is based on a carry lookahead tree implemented in negative logic, and with a strobed final sum circuit. Hardware measurements are presented, showing a 900 ps 58-bit incrementer delay.
Keywords
CMOS logic circuits; carry logic; logic gates; logic testing; sequential circuits; 58 bit; 900 ps; CMOS logic; SRCMOS; carry lookahead tree; level sensitive scan design compatible; negative logic; self resetting incrementer; self resetting logic register; strobed final sum circuit; test modes; CMOS logic circuits; Circuit testing; Coupling circuits; Delay; Hardware; Logic circuits; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3339-X
Type
conf
DOI
10.1109/VLSIC.1996.507699
Filename
507699
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