1V supply CMOS DEMUX for 40-GB/S optical communication systems

Author

Liang, Bangli ; Kwasniewski, Tad ; Chen, Dianyong ; Wang, Bo ; Cheng, Dezhong

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, ON

fYear

2008

fDate

24-26 June 2008

Firstpage

154

Lastpage

157

Abstract

A 1 V supply 1:2 demultiplexer (DEMUX) based on 0.13 mum CMOS technology is presented. It is designed for 40-Gb/s optical communication systems. This DEMUX achieved by a pair of master-slave flip-flops (MS-FFs) with opposite clock can operate at 40-Gb/s and beyond. Fully differential current mode logic (CML) is adopted to improve the bit rate of non-return-to-zero (NRZ) data stream and to suppress common mode disturbances. Output buffers for two outputs are employed to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors are used to boost the bandwidth. Stacked current source combined with low V_T (LVT) and regular V_T (RVT) NMOS is used so that the proposed DEMUX has good immunity against possible process, voltage and temperature (PVT) variations. This DEMUX IC dissipates a total current of 25 mA under a 1 V supply and consumes a chip area of 0.54 mm² with bonding pads.

Keywords

CMOS integrated circuits; demultiplexing equipment; flip-flops; integrated optoelectronics; optical communication equipment; CMOS DEMUX; bit rate 40 Gbit/s; common mode disturbances; current 25 mA; demultiplexer; fully differential current mode logic; master-slave flip-flops; non-return-to-zero data stream; on-chip shunt peaking; optical communication systems; output buffers; voltage 1 V; Bit rate; CMOS logic circuits; CMOS technology; Clocks; Flip-flops; Master-slave; Optical buffering; Optical design; Optical fiber communication; Optical signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2008 24th Biennial Symposium on

Conference_Location

Kingston, ON

Print_ISBN

978-1-4244-1945-6

Electronic_ISBN

978-1-4244-1946-3

Type

conf

DOI

10.1109/BSC.2008.4563227

Filename

4563227