Analysis and implementation of output voltage regulation in multi-phase switched capacitor converters

A new regulation technique based on duty cycle control of the average currents in the multi-phase switched capacitor converters (SCC) is proposed, analyzed, and verified experimentally for the No effective Charging (NC) case, also known as the fast switching limit (FSL). The regulation is accomplished by adjusting the value of the SCC equivalent resistor. To this end the time slots allotted to each of the SCC topologies are adjusted, while the total switching period is kept constant. The time slots are represented by master and slave duty cycles. By this, the SCC output voltage is expressed analytically as a function of the master duty cycle. In a similar way, analytical expressions for the voltages across the flying capacitors and for the average currents in each of the topologies can be obtained. Excellent agreement was found between the theoretical and experimental results.