DocumentCode
2123492
Title
System-level modeling and verification: a comprehensive design methodology
Author
Camurati, P. ; Corno, Fulvio ; Prinetto, P. ; Bayol, C. ; Soulas, B.
Author_Institution
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
fYear
1994
fDate
28 Feb-3 Mar 1994
Firstpage
636
Lastpage
640
Abstract
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level
Keywords
circuit CAD; logic CAD; CAD; description; system-level design methodology; system-level modeling; system-level verification; validation; Computer languages; Councils; Design for testability; Design methodology; Hardware; Protocols; Software libraries; Software tools; System-level design; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-5410-4
Type
conf
DOI
10.1109/EDTC.1994.326811
Filename
326811
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