DocumentCode :
2123641
Title :
Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems
Author :
Guangshuo Liu ; Jinpyo Park ; Marculescu, Diana
Author_Institution :
Dept. of ECE, Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2013
fDate :
6-9 Oct. 2013
Firstpage :
54
Lastpage :
61
Abstract :
This paper addresses the problem of dynamic thread mapping in heterogeneous many-core systems via an efficient algorithm that maximizes performance under power constraints. Heterogeneous many-core systems are composed of multiple core types with different power-performance characteristics. As well documented in the literature, the generic mapping problem is an NP-complete problem which can be formulated as a 0-1 integer linear program, therefore, prohibitively expensive to solve optimally in an online scenario. However, in real applications, thread mapping decisions need to be responsive to workload phase changes. This paper proposes an iterative approach bounding the runtime as O(n2/m), for mapping multi-threaded applications on n cores comprising of m core types. Compared with an optimal solution, the proposed algorithm produces results less than 0.6% away from optimum on average, with two orders of magnitude improvement in runtime. Results show that performance improvement can reach 16% under iso-power constraints compared to a random mapping. The algorithm can be brought online for hundred-core heterogeneous systems as it scales to systems comprised of 256 cores with less than one millisecond in overhead.
Keywords :
computational complexity; integer programming; linear programming; multi-threading; multiprocessing systems; performance evaluation; NP-complete problem; dynamic thread mapping; generic mapping problem; high-performance many-core systems; hundred-core heterogeneous systems; integer linear program; iso-power constraints; iterative approach; multithreaded applications; power-efficient heterogeneous many-core systems; power-performance characteristics; random mapping; workload phase changes; Benchmark testing; Heuristic algorithms; Instruction sets; Multicore processing; Power demand; Runtime; Throughput; Heterogeneous many-core; dynamic thread mapping; heuristic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2013 IEEE 31st International Conference on
Conference_Location :
Asheville, NC
Type :
conf
DOI :
10.1109/ICCD.2013.6657025
Filename :
6657025
Link To Document :
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