High-level design validation using algorithmic debugging

Author

Naganuma, Jim ; Ogura, Takeshi ; Hoshino, Tamio

Author_Institution

NTT LSI Labs., Kanagawa, Japan

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

474

Lastpage

480

Abstract

This paper proposes a new environment for high-level LSI design validation using “Algorithmic Debugging” and evaluates its benefits on three significant examples. A design is specified at a high-level using the structured analysis (SA) method and some errors included in SA specifications are efficiently located by answering just a few queries from the debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. This environment promises to be an important step towards efficient high-level LSI design validation

Keywords

VLSI; circuit CAD; integrated logic circuits; large scale integration; logic CAD; program debugging; CAD; LSI design validation; algorithmic debugging; high-level design validation; structured analysis; Acceleration; Algorithm design and analysis; Automatic logic units; Debugging; Hardware design languages; Large scale integration; Real time systems; Software engineering; Standardization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326833

Filename

326833