Author :
McCoy, Bernard A. ; Robins, Gabriel
Author_Institution :
Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
fDate :
28 Feb-3 Mar 1994
Abstract :
An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e. it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e. where cycles are admissible). We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon. Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters. Finally, we observe that non-tree routing also significantly reduces signal skew
Keywords :
SPICE; circuit layout CAD; graph theory; network routing; network topology; LDRG algorithm; SPICE; Steiner routing; arbitrary graphs; nontree routing topology; optimal routing graph; routing algorithm; signal net; signal propagation delay; signal skew; total wirelength increase; wire capacitance/resistance tradeoff; Capacitance; Computer science; Integrated circuit interconnections; Propagation delay; Routing; SPICE; Topology; Tree graphs; Very large scale integration; Wires;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326840