Cell height driven transistor sizing in a cell based module design

We consider the transistor sizing problem in a module layout which consists of several rows of automatically generated leaf cells based on a new layout style proposed by Hwang et al. (1991). The sizing is performed in two levels. At the module level, a leaf cell is chosen based on a height slack (usable area) and timing slack. At the cell level, the cell is sized based on a width constraint imposed from the module level. The problem of sizing a cell is formulated as a nonlinear program. The objective is to minimize the difference of actual arrival time and the required time of all output nodes simultaneously. A benchmarking process has been conducted at both cell level and module level. Experiments on a set of cells show that on the average over 25% performance improvement is obtained by using 0.06% more area. Moreover, for a leaf cell with multiple outputs, the sizer can indeed simultaneously make the arrival time of all output nodes close to the required time. Results of a module level experiment show that using height slack the maximum delay of the circuit can be reduced up to 17.7% without area penalty for the example shown