Test of bridging faults in scan-based sequential circuits

An I_DDQ testing strategy combined with logical scan-out observation for bridging faults in scan-based sequential circuits is presented. Internal and external zero resistance bridging faults in both the combinational part and the scan path are considered. The testing strategy targets the faults beginning with those harder to detect. Thus, combinational internal shorts and combinational external shorts are targeted first. Remaining external shorts in the scan path are considered later. A standard ATPG for stuck-at faults, adapted to short fault detection, is used. In order to reduce the test application time, the time to apply I_DDQ test vectors and the time to produce a shift in the scan chain is taken into account. Results of the experimentation on ISCAS´89 circuits show that the strategy provides high quality test sets of reduced size with the highest obtainable coverages for both internal and external shorts