Title :
Transforming sequential logic in digital CMOS ICs for voltage and I DDQ testing
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
28 Feb-3 Mar 1994
Abstract :
To ensure the functionality, quality and reliability of digital CMOS ICs, the conventional logic testing and IDDQ testing are recognized as absolute test requirements. However, some of the bridging defects in sequential circuits are not detected by IDDQ. Furthermore, for complex devices, even scan based logic testing can be expensive. In this paper, a new concept of transforming sequential logic into purely combinational logic is described. With the help of the proposed method complete sequential logic is voltage and IDDQ tested in four test vectors
Keywords :
CMOS integrated circuits; circuit reliability; combinatorial circuits; flip-flops; integrated logic circuits; logic testing; sequential circuits; IDDQ testing; bridging defect detection; combinational logic; digital CMOS ICs; flip flop; functionality; reliability; sequential logic transformation; test vectors; voltage testing; CMOS logic circuits; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Logic devices; Logic testing; Sequential analysis; Voltage;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326851
