Speed and area analysis of memory based FFT processors in a FPGA

Author

Yeh, Hen Geul ; Truong, Gerald

fYear

2007

fDate

26-28 April 2007

Firstpage

1

Lastpage

6

Abstract

In this paper we present a trade-off analysis between hardware size and speed performance, measured in clock cycles, concerning fixed-point, memory-based FFT processors designed for FPGA. For OFDM systems using fixed-point FFT processors we also provide bit width requirements for different FFT sizes and digital modulation schemes including QPSK, 16-QAM, 64-QAM, 256-QAM. The information provided is based on six individual FFT processors which were modeled in software using the Java programming language, designed in HDL using Verilog and implemented in hardware using the Xilinx Spartan-3 FPGA.

Keywords

Java; OFDM modulation; digital arithmetic; fast Fourier transforms; field programmable gate arrays; hardware description languages; logic CAD; microprocessor chips; quadrature amplitude modulation; quadrature phase shift keying; HDL; Java programming language; OFDM systems; QAM; QPSK; Verilog; Xilinx Spartan-3 FPGA; digital modulation; fixed-point memory based FFT processor design; Clocks; Digital modulation; Field programmable gate arrays; Hardware design languages; OFDM; Performance analysis; Process design; Quadrature phase shift keying; Size measurement; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Telecommunications Symposium, 2007. WTS 2007

Conference_Location

Pomona, CA

ISSN

1934-5070

Print_ISBN

978-1-4244-0696-8

Electronic_ISBN

1934-5070

Type

conf

DOI

10.1109/WTS.2007.4563313

Filename

4563313