Practical verification of power delivery networks for smart TV applications

This paper introduces a practical methodology to improve power integrity performance of the chip-package-PCB systems for smart TVs. For power integrity analysis, a chip, package and PCB are modeled as lumped element circuits for simplicity. Case studies are presented to optimize MLCC placement using chip-package-PCB co-simulation under fixed SoC design. In case studies, CPU power net of an application processor is chosen, and voltage droop is measured as a design weight on each physical domains. The introduced methodology is evaluated through experimental verifications.