Title :
Towards incorporating device parameter variations in timing analysis
Author :
Sivaraman, Mukund ; Satrojwas, A.J.
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
fDate :
28 Feb-3 Mar 1994
Abstract :
Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations-caused by the imperfect fabrication process-which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance
Keywords :
circuit analysis computing; combinatorial circuits; logic CAD; circuit simulation; combinational circuits; correlated component delay models; device parameter variations; imperfect fabrication process; logic design; maximum true delay; space exploration; timed path sensitization; timing analysis; timing verification mechanism; worst-case instance; Circuit simulation; Circuit synthesis; Circuit testing; Clocks; Delay; Digital circuits; Fabrication; Independent component analysis; Robustness; Timing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326855
