• DocumentCode
    21245
  • Title

    Structure-Aware Placement Techniques for Designs With Datapaths

  • Author

    Ward, Samuel I. ; Myung-Chul Kim ; Viswanathan, Natarajan ; Zhuo Li ; Alpert, Charles J. ; Swartzlander, Earl E. ; Pan, David Z.

  • Author_Institution
    Univ. of Texas, Austin, TX, USA
  • Volume
    32
  • Issue
    2
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    228
  • Lastpage
    241
  • Abstract
    As technology scales and frequencies increase, a new hybrid design style emerges, wherein designs contain a mixture of random logic and datapath standard-cell components. This paper demonstrates that conventional half-perimeter wirelength driven placers underperform in terms of regularity and Steiner wirelength (StWL) for such hybrid designs. In addition, the quality gap between manual and automatic placement is more pronounced as the designs become more datapath oriented. To effectively handle hybrid designs, this paper proposes a new unified placement flow that simultaneously places random logic and datapath cells. This flow is built on the top of a leading academic force-directed placer and significantly improves the quality of datapath placement while leveraging the speed and flexibility of existing random-logic placement algorithms. It consists of a suite of novel global and detailed placement techniques, collectively called structure-aware placement techniques (SAPT). These techniques effectively integrate alignment constraints into placement, thereby overcoming the deficiencies of existing random-logic placers when handling designs with embedded datapaths. Compared to other state-of-the-art placers, SAPT improves total StWL by more than 28% and total routing overflow by over six times on the ISPD 2011 datapath benchmark suite. In addition, it improves total StWL by 5.8% on industrial hybrid designs.
  • Keywords
    logic circuits; logic design; ISPD 2011 datapath benchmark suite; StWL; Steiner wirelength; academic force-directed placer; alignment constraints; automatic placement; datapath placement quality; datapath standard-cell components; embedded datapaths; half-perimeter wirelength; industrial hybrid designs; manual placement; random-logic placement algorithms; routing overflow; structure-aware placement techniques; unified placement flow; Benchmark testing; Latches; Layout; Measurement; Optimization; Pins; Routing; Algorithms; datapath; layout; optimization; physical design; placement;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2012.2233862
  • Filename
    6416106