DocumentCode :
2124674
Title :
Voltage scaling on C-elements: A speed, power and energy efficiency analysis
Author :
Trevisan Moreira, Matheus ; Laert Vilar Calazans, Ney
Author_Institution :
Hardware Design Support Group (GAPH), Pontifical Catholic Univ. of Rio Grande do Sul (PUCRS), Porto Alegre, Brazil
fYear :
2013
fDate :
6-9 Oct. 2013
Firstpage :
329
Lastpage :
334
Abstract :
This work reports an evaluation of speed, energy consumption, leakage power, and silicon area tradeoffs of three different transistors topologies for C-elements, basic devices for building asynchronous circuits. The evaluation considers the devices operating under supply voltages that vary from nominal IV to 0.05V. Analog simulations provide precise measurements and the obtained results identify the lowest voltage at which each C-element operates correctly. Results suggest that operating at near-threshold voltages provides the best speed-energy and speed-leakage efficiencies. Also, they point the van Berkel topology as the most suited C-element implementation for low voltage operation, as it presents lower power and energy figures as well as higher speed, regardless of the supply voltage.
Keywords :
asynchronous circuits; power aware computing; transistors; C-element implementation; asynchronous circuit; energy consumption; leakage power; near-threshold voltage; silicon area tradeoff; speed-energy efficiency; speed-leakage efficiency; transistor topology; van Berkel topology; voltage 1 V to 0.05 V; voltage scaling; Decision support systems; C-element; leakage power reduction; low power design; low voltage; voltage scaling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2013 IEEE 31st International Conference on
Conference_Location :
Asheville, NC
Type :
conf
DOI :
10.1109/ICCD.2013.6657061
Filename :
6657061
Link To Document :
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