PCB layout optimization using external LDO for low EMI

Author

Seung-Hee Ryu ; Seung-Baek Park ; Soo-won Kim

Author_Institution

Samsung Electron., Suwon, South Korea

fYear

2015

fDate

9-12 Jan. 2015

Firstpage

610

Lastpage

611

Abstract

LDOs are useful since LDOs do not generate switching noise, while synchronous DC-DC buck converters do. Because of this advantage, it is easy for designers to ignore the importance of the system-level PCB layout design. To control EMI at the output terminal of an LDO, the proper PCB layout is essential. This paper evaluates two types of power trace layouts for LDO test benches with a 10-layer stack-up PCB. Time-domain measurement of voltage at the output terminal of an LDO and an acoustic measurement were performed for the evaluation. The voltage drop decreased by 65 mV after the layout of the linear regulator output was revised.

Keywords

acoustic measurement; circuit optimisation; electromagnetic interference; printed circuit layout; voltage measurement; voltage regulators; EMI; PCB layout optimization; acoustic measurement; external low dropout voltage regulators; linear regulator output; time-domain voltage measurement; Acoustic measurements; Cameras; Electromagnetic interference; Layout; Noise; Voltage control; Voltage measurement; EMI reduction; LDO; System-level PCB layout;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ICCE), 2015 IEEE International Conference on

Conference_Location

Las Vegas, NV

Print_ISBN

978-1-4799-7542-6

Type

conf

DOI

10.1109/ICCE.2015.7066548

Filename

7066548