PCB layout optimization using external LDO for low EMI

LDOs are useful since LDOs do not generate switching noise, while synchronous DC-DC buck converters do. Because of this advantage, it is easy for designers to ignore the importance of the system-level PCB layout design. To control EMI at the output terminal of an LDO, the proper PCB layout is essential. This paper evaluates two types of power trace layouts for LDO test benches with a 10-layer stack-up PCB. Time-domain measurement of voltage at the output terminal of an LDO and an acoustic measurement were performed for the evaluation. The voltage drop decreased by 65 mV after the layout of the linear regulator output was revised.