High speed photon counting readout ASIC for spectral computed tomography detectors

This study presents a design of a high-speed photon counting readout circuit for spectral computed tomography detectors. We propose a novel front-end architecture aimed to reduce a dead time by introducing dual signal paths in each pixel. A prototype chip is fabricated with 0.18um six-metal standard CMOS process that consists of 16 × 16 pixels and periphery circuits. Each pixel has 200um pixel pitch and contains two signal paths. The switching circuit in the pixel allows a single signal path to connect with the input pad at a time. As a result, the proposed dual-path readout scheme shows a 3-times higher speed than that of a conventional single-path readout scheme.