A VLSI implementation of parallel fast Fourier transform

Author

Vacher, A. ; Benkhebbab, M. ; Guyot, A. ; Rousseau, T. ; Skaf, A.

Author_Institution

TIMA Lab., CNRS, Grenoble, France

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

250

Lastpage

255

Abstract

This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations

Keywords

VLSI; digital arithmetic; digital signal processing chips; fast Fourier transforms; hypercube networks; logic design; parallel architectures; pipeline processing; VLSI circuit design; VLSI implementation; cost effective butterfly operator; folded pipeline; on-line most-significant-digit-first arithmetic; on-line operators; operator merging rules; parallel fast Fourier transform; pipelined fast Fourier transform; Costs; Digital signal processing; Fast Fourier transforms; Fourier transforms; Laboratories; Legged locomotion; Merging; Multiplexing; Pipelines; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326869

Filename

326869