PLFP256 a pipelined Fourier processor

Author

Coulomb, Pierre ; Pogodalla, Francois

Author_Institution

ENSERG, Grenoble, France

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

245

Lastpage

249

Abstract

This paper presents a fast Fourier transform ASIC designed to be used on a DSP expansion board for a PC. From specification to test all steps in the ASIC design were made by 3rd year engineering school students. This project formed part of the practical work of the ASIC design courses in the ENSIMAG/ENSERG Architecture Department. The final chip implements the direct and reverse FFT algorithms, external buses arbitration, host interface, converters and memory management. Running at 25 MHz, this 30000 transistor ASIC can perform realtime signal processing on 44 kHz sample rate audio signals

Keywords

CMOS integrated circuits; acoustic signal processing; application specific integrated circuits; digital arithmetic; digital signal processing chips; fast Fourier transforms; logic design; pipeline processing; storage management; 25 MHz; 3rd year engineering school students; 44 kHz; ASIC design; DSP expansion board; ENSIMAG/ENSERG Architecture Department; PC; PLFP256; converters; external buses arbitration; fast Fourier transform ASIC; host interface; memory management; pipelined Fourier processor; realtime signal processing; reverse FFT algorithms; sample rate audio signals; Algorithm design and analysis; Application specific integrated circuits; CMOS technology; Design engineering; Digital signal processing chips; Fast Fourier transforms; Memory management; Signal design; Signal processing algorithms; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326870

Filename

326870