Title :
Modeling of broken connections faults in CMOS ICs
Author :
Favalli, Michele ; Dalpasso, Marcello ; Olivo, Piero ; Riccò, Burno
Author_Institution :
Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
fDate :
28 Feb-3 Mar 1994
Abstract :
This work presents a fault model to effectively account for broken connections inside CMOS circuits. The proposed model is very general, since it allows one to detect broken connections that cannot be individualized by means of test sequences for stuck-open faults; in addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node. Conditions for the detection of broken connections are derived from electrical considerations and the minimum number of input vectors to be applied to test for a broken connection in a node is determined by graph theory. The model can be used to derive tests and to perform fault simulations independently of the actual layout of the circuit
Keywords :
CMOS integrated circuits; fault location; graph theory; integrated circuit testing; integrated logic circuits; logic testing; CMOS ICs; IC testing; broken connection faults; fault model; fault simulations; graph theory; stuck-open faults; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit layout; Integrated circuit modeling; Integrated circuit testing; Semiconductor device modeling; System testing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326882
