DocumentCode
2125220
Title
An OBDD-representation of statecharts
Author
Helbig, Johannes ; Kelb, Peter
Author_Institution
Dept. of Comput. Sci., Oldenburg Univ., Germany
fYear
1994
fDate
28 Feb-3 Mar 1994
Firstpage
142
Lastpage
149
Abstract
We present an effective method to translate a statechart into an ordered binary decision diagram (OBDD) representation of its transition system. By that it becomes possible to verify a system specified by a statechart by symbolic model checking, one of the most advanced automatic verification techniques. The method exploits the hierarchy in the relevance of information as is implied by the state structure and admits some redundancy to keep the “decoding effort” of each OBDD small. The method is implemented in the ESPRIT project FORMAT, where OBDD based transition systems serve as a common ground to verify specifications in VHDL or (a variant of) statecharts against temporal logic, symbolic timing diagrams, and each other
Keywords
Boolean functions; diagrams; encoding; finite state machines; formal verification; logic CAD; specification languages; ESPRIT project; FORMAT; OBDD based transition systems; OBDD-representation; VHDL; automatic verification technique; ordered BDD; ordered binary decision diagram; redundancy; specifications verification; statecharts; symbolic model checking; Automatic logic units; Petri nets; State-space methods; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-5410-4
Type
conf
DOI
10.1109/EDTC.1994.326884
Filename
326884
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