CMOS integrated circuit for power-line interference reduction in biopotential measurements

Author

Silva, Ivan S S ; Naviner, Jean-François ; Freire, Raimundo C.

Author_Institution

Univ. Fed. do Para, Belem

fYear

2006

fDate

20-21 April 2006

Firstpage

6

Lastpage

9

Abstract

During biopotential signal measurement, noise due to electrical power-line network frequently appears as common-mode signal on electrodes connecting the patient to measurement instruments. In this case, because of mismatch of coupling impedances coupling between patient skin and electrodes and also because of differential amplifier non-idealities, a signal at power network frequency is present at the amplifier output. In this paper, we present a CMOS integrated circuit implementing a biopotential electrodes mismatch impedance compensation scheme, using an impedance digital controller. Circuit architecture, design and simulation results based on MOS transistor models are presented and discussed

Keywords

CMOS integrated circuits; MOSFET; bioelectric potentials; biomedical electrodes; biomedical electronics; biomedical measurement; differential amplifiers; impedance matching; skin; CMOS integrated circuit; MOS transistor model; biopotential electrodes; biopotential signal measurement; common-mode signal; differential amplifier; electrical power-line network; impedance compensation scheme; impedance coupling; impedance digital controller; impedance mismatch compensation technique; patient skin; power network frequency; power-line interference reduction; CMOS integrated circuits; Coupling circuits; Differential amplifiers; Electric variables measurement; Electrodes; Impedance; Integrated circuit measurements; Integrated circuit noise; Interference; Noise measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Medical Measurement and Applications, 2006. MeMea 2006. IEEE International Workshop on

Conference_Location

Benevento

Print_ISBN

1-4244-0253-0

Type

conf

DOI

10.1109/MEMEA.2006.1644447

Filename

1644447