Efficient Scheduling Algorithms for MpSoC Systems

Author

Tafesse, Bisrat ; Raina, Ashwini ; Suseela, Jaya ; Muthukumar, Venkatesan

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Nevada Las Vegas, Las Vegas, NV, USA

fYear

2011

fDate

11-13 April 2011

Firstpage

683

Lastpage

688

Abstract

MpSoCs have been proposed as a viable solution for present day application, which requires a growing demand in data processing and real-time processing with power constraints. Scheduling and Mapping are two important steps in the MpSoC design process that facilitates efficient MpSoC System. This work presents two scheduling algorithms: (1) Performance Driven Scheduling (PDS) Algorithm (for bus-based MpSoC) and (2) Traffic Aware Scheduling (TAS) algorithm (for NoC-based MpSoC). The algorithms are tested on synthetic task graphs and their performances are evaluated and discussed.

Keywords

graph theory; multiprocessing systems; processor scheduling; real-time systems; system-on-chip; task analysis; MpSoC design process; data processing; performance driven scheduling algorithm; power constraint mapping; power constraint scheduling; real-time processing; synthetic task graph; traffic aware scheduling algorithm; Algorithm design and analysis; Optimal scheduling; Program processors; Scheduling; Scheduling algorithm; Topology; Mapping; MpSoCs; Scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology: New Generations (ITNG), 2011 Eighth International Conference on

Conference_Location

Las Vegas, NV

Print_ISBN

978-1-61284-427-5

Electronic_ISBN

978-0-7695-4367-3

Type

conf

DOI

10.1109/ITNG.2011.121

Filename

5945319