Title :
Introduction of permissible bridges with application to logic optimization after technology mapping
Author :
Rohfleisch, Bernhard ; Brglez, Franc
Author_Institution :
Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
fDate :
28 Feb-3 Mar 1994
Abstract :
This paper introduces the concept of a permissible bridge and a permissible bridge pair. A bridge is a logic node with two inputs and one output. A bridge or a bridge pair are called permissible if they can be inserted into a Boolean network without changing its behavior at primary outputs. There are a total of 255 types of bridges that can be considered between any pair of wires in the network. We discuss a subset of such bridges and present three theorems related to permissible bridges for pairwise detectability, distinguishability and conditional equivalence. Experimental results show that relatively many bridges are permissible in each circuit. In this paper, we exploit the conditional equivalence of wire pairs and show that even after technology mapping, we can significantly reduce the active area as well as the wiring of many designs
Keywords :
Boolean functions; circuit layout; combinatorial circuits; directed graphs; logic design; logic testing; Boolean network; active area reduction; combinational circuit; conditional equivalence; directed acyclic network graph; fault diagnosis; logic node; logic optimization; multiple fault test generation; pairwise detectability; pairwise distinguishability; permissible bridge pair; permissible bridges; technology mapping; wire pairs; Bridge circuits; Circuit synthesis; Delay; Design optimization; Electronic design automation and methodology; Libraries; Logic design; Logic testing; Wires; Wiring;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326893