Title :
A board level parallel test and short circuit failure repair circuit for high-density, low-power DRAMs
Author :
Furutani, K. ; Ooishi, T. ; Asakura, M. ; Hidaka, H. ; Ozaki, H.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
The authors present a board level parallel test circuit which greatly increases the throughput of test operations for high-density DRAMs. Also described is a short circuit failure repair circuit which enhances the yield of super low power DRAMs. They are both useful for the manufacturing of high-density, low-power DRAMs.
Keywords :
DRAM chips; VLSI; integrated circuit testing; integrated circuit yield; leakage currents; production testing; DRAM testing; board level parallel test circuit; dynamic RAM; high-density DRAMs; low-power DRAMs; manufacturing; short circuit failure repair circuit; yield enhancement; Circuit testing; Manufacturing; Throughput;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507720
