TORSIM: An efficient fault simulator for synchronous sequential circuits

Author

Gai, S. ; Montessoro, P.L. ; Reorda, M. Sonza

Author_Institution

Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

46

Lastpage

50

Abstract

The paper describes a new approach to the fault simulation of synchronous sequential circuits. Its novelty comes from combining the event-driven compiled-code simulation technique proposed by H. K. Lee and D. S. Ha (1992) with the single fault propagation fault-parallel fault simulation algorithm used by F. Maamari and J. Rajski (1988). Our approach is particularly suited for those applications requiring the fault simulation of very high numbers of input patterns, like signature computation or fault dictionary construction. A fault simulator named TORSIM has been written to verify the effectiveness of the approach. The results we present show an average speed-up in terms of CPU time of more than one order of magnitude with respect to the ones reported by Maamari and Rajski

Keywords

circuit analysis computing; logic CAD; logic testing; sequential circuits; TORSIM; event-driven compiled-code simulation; fault dictionary construction; fault simulation algorithm; fault simulator; parallel fault; signature computation; single fault propagation; synchronous sequential circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Design automation; Discrete event simulation; Life testing; Sequential circuits; System testing; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326900

Filename

326900