A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter

Author

Singer, L.A. ; Brooks, T.L.

Author_Institution

Analog Devices Inc., Wilmington, MA, USA

fYear

1996

fDate

13-15 June 1996

Firstpage

94

Lastpage

95

Abstract

A 14-bit 10-MHz sampling analog-to-digital converter has been realized without calibration in a double-poly 0.8 /spl mu/m CMOS process. The ADC utilizes a 4-stage pipelined architecture with a wide-band sample-and-hold amplifier and achieves the highest resolution reported to date at 10 MHz. The chip occupies a die area of 19 mm/sup 2/, uses a single 5 V supply voltage, and dissipates only 210 mW. Measured DNL and INL are /spl plusmn/0.7 LSB and /spl plusmn/2.5 LSB, respectively. The SNR and THD for a 1 MHz input signal are 81 dB and -87 dB, respectively.

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.8 micron; 10 MHz; 14 bit; 210 mW; 5 V; DNL; INL; SNR; THD; calibration-free A/D converter; die area; double-poly CMOS process; pipelined architecture; power dissipation; sampling analog-to-digital converter; wide-band sample-and-hold amplifier; Analog-digital conversion; Broadband amplifiers; CMOS process; Calibration; Sampling methods; Semiconductor device measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507727

Filename

507727