Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library

Author

Greiner, A. ; Lucas, L. ; WajsbÜrt, E. ; Winckel, L.

Author_Institution

Lab. MASI, Univ. Pierre et Marie Curie, Paris, France

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

9

Lastpage

13

Abstract

This paper presents the design flow for a superscalar VLIW microprocessor using the 0.8 μ CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A full set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle and to maintain a high level of integration and performance. The final circuit contains about 875000 transistors with a die size of 14.6×14.6 mm². The chip design and verification have been performed with new advanced CAD tools developed in the IDPS project. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; microprocessor chips; parallel machines; pipeline processing; reduced instruction set computing; 0.8 mum; 32 bit; 428-pin PGA package; CAD tools; CMOS portable ASIC library; ESPRIT2 IDPS project; RISC architecture; cell libraries; chip design; chip verification; design flow; layout; macro-block generators; portable IDPS ASIC library; superscalar VLIW microprocessor; symbolic approach; three-stage pipeline; top-down design methodology; Application specific integrated circuits; CMOS technology; Clocks; Design automation; Hardware; Libraries; Microprocessors; Registers; Scheduling; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326906

Filename

326906