CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC

A CMOS ADC architecture is presented that combines pipelined low pass ADCs with time interleaving to obtain sampling frequencies in the 3 to 6 GHz range with bandwidths of 1.5 to 3 GHz and 10-12 bits of resolution. The schematic design and performance simulations are included for a 180 nm CMOS process. The Time Interleaved Pipelined (TIP) ADC samples at 3.2 GHz with inputs in either the first or second Nyquist region and has 12 bits resolution while consuming 900 mW of power with 1.8 v power supply.