DocumentCode :
2125770
Title :
CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC
Author :
Ren, Saiyu ; Siferd, Ray
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
fYear :
2011
fDate :
11-13 April 2011
Firstpage :
785
Lastpage :
790
Abstract :
A CMOS ADC architecture is presented that combines pipelined low pass ADCs with time interleaving to obtain sampling frequencies in the 3 to 6 GHz range with bandwidths of 1.5 to 3 GHz and 10-12 bits of resolution. The schematic design and performance simulations are included for a 180 nm CMOS process. The Time Interleaved Pipelined (TIP) ADC samples at 3.2 GHz with inputs in either the first or second Nyquist region and has 12 bits resolution while consuming 900 mW of power with 1.8 v power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS ADC architecture; CMOS process; Nyquist region; bandwidth 1.5 GHz to 3 GHz; bit time interleaved pipelined ADC; frequency 3 GHz to 6 GHz; pipelined low pass ADC; power 900 mW; sampling frequency; size 180 nm; voltage 1.8 V; Bandwidth; CMOS integrated circuits; Clocks; Delay; Frequency division multiplexing; Generators; Time frequency analysis; CMOS low pass ADC; circular buffer; high resolution; time interleaving; wide bandwidth;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Technology: New Generations (ITNG), 2011 Eighth International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-61284-427-5
Electronic_ISBN :
978-0-7695-4367-3
Type :
conf
DOI :
10.1109/ITNG.2011.137
Filename :
5945336
Link To Document :
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