Title :
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC
fDate :
Feb. 28 1994-March 3 1994
Abstract :
The following topics were dealt with: processor architecture; system level transformation and micro code generators; sequential circuit testing; system design and mixed A/D synthesis;circuit optimization and partitioning; BIST techniques; finite state machine verification; fault modeling; synchronous finite state machines; BDD concepts; boundary scan applications;DSP implementations; algorithmic transformations in high-level synthesis; DFT for delay faults and sequential machines; estimation during high-level synthesis; statistical and high-level timing analysis; bridging faults in testing; specification and synthesis of system interfaces; routing; testing efficiency; system-level design methodologies; scheduling in high-level synthesis; analogue system design; logic, circuit, and yield simulation; DFT for datapaths, controllers, and arrays; high-level verification
Keywords :
analogue circuits; application specific integrated circuits; boundary scan testing; built-in self test; computer architecture; design for testability; digital signal processing chips; finite state machines; integrated circuit testing; logic CAD; logic arrays; logic design; logic testing; microprocessor chips; mixed analogue-digital integrated circuits; network routing; sequential circuits; sequential machines; BDD concepts; BIST techniques; DFT; DSP implementations; algorithmic transformations; analogue system design; arrays; binary decision diagrams; boundary scan applications; bridging faults; circuit optimization; controllers; datapaths; delay faults; fault modeling; finite state machine verification; high-level synthesis; high-level timing analysis; high-level verificati; logic simulation; micro code generators; mixed A/D synthesis; partitioning; processor architecture; routing; scheduling; sequential circuit testing; sequential machines; statistical timing analysis; synchronous finite state machines; system design; system interfaces; system level transformation; system-level design methodologies; testing efficiency; yield simulation;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris, France
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326908
