DocumentCode :
2125808
Title :
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
Author :
Islam, Mafijul Md
Author_Institution :
Chalmers Univ. of Technol., Goteborg
fYear :
2007
fDate :
24-27 Oct. 2007
Firstpage :
54
Lastpage :
61
Abstract :
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. However, the achievable performance to commensurate the actual potential of TLS is limited by the thread-management overhead. In this paper, we have exploited the run-time behavior of the performance-critical loops to minimize such overhead to improve the performance using embedded applications. We have shown that an average speedup of 2.4 is achievable on a 4-way machine which supports TLS, but has no special mechanism to predict the loop trip count. Then we have augmented the machine with the perfect knowledge of the loop trip count and obtained an average speedup of 2.6. Finally, we have incorporated a simple stride predictor to predict the loop trip count dynamically. The proposed predictor has an average prediction accuracy of 96% and the machine then yields an average speedup of 2.5 for the chosen applications.
Keywords :
microprocessor chips; multi-threading; loop termination; speculative thread-level parallelism; thread-management overhead; Accuracy; Application software; Computer architecture; Computer science; Hardware; High performance computing; Parallel processing; Program processors; Runtime; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture and High Performance Computing, 2007. SBAC-PAD 2007. 19th International Symposium on
Conference_Location :
Rio Grande do Sul
ISSN :
1550-6533
Print_ISBN :
978-0-7695-3014-7
Type :
conf
DOI :
10.1109/SBAC-PAD.2007.23
Filename :
4384042
Link To Document :
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