Clock skew minimization with adjustable delay buffers restriction

Multiple dynamic supply voltage (MDSV) designs can be used to reduce power consumption. However, switching of power modes may cause increasing of the clock skew because some modules operate with different voltages. In this paper, the adjustable delay buffers (ADBs) is used to minimize clock skew under different power modes. We first construct a clock tree to assign positions of adjustable delay buffers. Because adjustable delay buffers can increase additional delays, the clock skew can be optimized. It is unlikely to add an unlimited number of ADBs in real world so the number of ADBs must be limited. If the number of ADBs is not satisfied with the constraints in the previous solution, a bottom-up method is then used to remove some adjustable delay buffers. Finally, the experimental results show that the presented algorithms generate effective improvements.