DocumentCode
2125936
Title
A 960 Mbps/pin interface for skew-tolerant bus using low jitter PLL
Author
Sungjoon Kim ; Kyeongho Lee ; Yongsam Moon ; Deog-Kyoon Jeong ; Yunho Choi ; Hyung Kyu Lim
Author_Institution
Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., South Korea
fYear
1996
fDate
13-15 June 1996
Firstpage
118
Lastpage
119
Abstract
This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two experimental chips with 4 pin interface have been fabricated with 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mbps per pin.
Keywords
CMOS digital integrated circuits; VLSI; clocks; jitter; phase locked loops; 0.6 micron; 960 Mbit/s; CMOS technology; I/O scheme; high-speed bus; low jitter PLL; oversampling method; skew-tolerant bus; supply noise; Bandwidth; CMOS technology; Circuit noise; Clocks; Jitter; Phase locked loops;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3339-X
Type
conf
DOI
10.1109/VLSIC.1996.507737
Filename
507737
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