Title :
A 156 Mbps CMOS clock recovery circuit for burst-mode transmission
Author :
Nakamura, Mitsutoshi ; Ishihara, N. ; Akazawa, Y.
Author_Institution :
NTT LSI Labs., Kanagawa, Japan
Abstract :
This paper describes a new timing circuit design technique for asynchronous burst-mode data transmission, such as Fiber To The Home (FTTH). Without external reference clock signals, it enables the quick extraction of clock signal from received NRZ data packets using a "gating timing circuit" and "burst PLL". The circuit\´s simple configuration reduces both size and power. A fabricated 0.5-/spl mu/m CMOS IC exhibits instantaneous response within one bit for 156 Mbps asynchronous data packets.
Keywords :
CMOS digital integrated circuits; clocks; optical fibre subscriber loops; packet switching; phase locked loops; synchronisation; timing circuits; 0.5 micron; 156 Mbit/s; CMOS; FTTH; NRZ data packets; asynchronous burst-mode data transmission; burst PLL; clock recovery circuit; gating timing circuit; instantaneous response; timing circuit design; CMOS integrated circuits; Circuit synthesis; Clocks; Data communication; Data mining; Optical fiber subscriber loops; Optical signal processing; Timing;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507739
