DocumentCode :
21260
Title :
SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning
Author :
Yan, J.Z. ; Chu, Chris
Author_Institution :
Placement Technol. Group, Cadence Design Syst., Inc., San Jose, CA, USA
Volume :
32
Issue :
2
fYear :
2013
fDate :
Feb. 2013
Firstpage :
175
Lastpage :
188
Abstract :
This paper presents an efficient, scalable, and optimal slack-driven shaping algorithm for soft blocks in nonslicing floorplan. The proposed algorithm is called SDS. SDS is specifically formulated for fixed-outline floorplanning. Given a fixed upper bound on the layout width, SDS minimizes the layout height by only shaping the soft blocks in the design. Iteratively, SDS shapes some soft blocks to minimize the layout height with the guarantee that the layout width would not exceed the given upper bound. Rather than using some simple heuristic as in previous work, the amount of change on each block is determined by systematically distributing the global total amount of available slack to individual block. During the whole shaping process, the layout height monotonically reduces and eventually converges to an optimal solution. Two optimality conditions are presented to check the optimality of a shaping solution for fixed-outline floorplanning. In practice, to terminate the process of convergence early, we propose two different stopping criteria. We also extend SDS to handle other floorplanning problems, e.g., classical floorplanning. To validate the efficiency and effectiveness of SDS, comprehensive experiments are conducted on MCNC and HB benchmarks. Compared with previous work, SDS achieves the best experimental result with a significantly faster runtime.
Keywords :
circuit optimisation; integrated circuit layout; HB benchmarks; MCNC benchmarks; SDS; fixed upper bound; fixed-outline floorplanning; layout height; layout width; nonslicing floorplan; optimal slack-driven block shaping; optimal solution; scalable slack-driven shaping; simple heuristic; soft blocks; stopping criteria; Algorithm design and analysis; Benchmark testing; Convergence; Layout; Shape; Upper bound; WiMAX; Block shaping; fixed-outline floorplanning; very large scale integration physical design;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2012.2228304
Filename :
6416107
Link To Document :
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