A 2 ns access, 500 MHz 288 Kb SRAM macro

High speed level-1 cache applications demand fast single cycle access times and short cycles. Novel circuits that deliver fast access times and self-resetting CMOS (SRCMOS) techniques that deliver fast cycle times are described. Two key elements for fast access times are: fast signal conversion from static CMOS to SRCMOS and fast signal conversion from SRCMOS to static CMOS. These conversions are performed by the input receiver and output driver circuits. A two-stage address decode scheme to minimize gate complexity and a high performance "late select 4-to-1" mux in front of the output drivers are also key elements. A "Sense and Hold Amplifier" (SHA) is used to perform pulse alignment with the asynchronous "late select" signal. The critical redundancy compare path is designed to be as fast as the primary word line decode path in order to minimize any impact on performance. SRCMOS circuitry allows for fast cycle operation without the use of a centrally controlled clocking scheme. Only the receivers are clocked and all subsequent circuits are triggered by pulses generated from preceding stages. Extensive sharing of reset circuitry is employed to minimize the overhead of SRCMOS. The SRAM includes a programmable "Array-Built-In-Self-Test" (ABIST) sub-macro which allows extensive test pattern coverage and access time evaluation at cycle speed.