Title :
A 500 MHz 1 Mb on-chip cache design using multi-level bit line sensing scheme
Author :
Guo, R. ; Su, T.Y. ; Chia-Chi Chao
Author_Institution :
Silicon Graphics Comput. Syst., Mountain View, CA, USA
Abstract :
The article compares the overall delay between a conventional design scheme vs. this work for the same process technology. Separate write BLs and split read BLs reduce the first two timing components from 22 gd to 10 gd. A new SA design improves the sensing delay by 3 gd, and the differential dynamic implementation of sel mux/load aligner shaves 5 more gd from critical path. Therefore we conclude this design using multi-level sensing scheme can reduce 40 gd cycle time by conventional scheme down to 20 gd, achieving 500 MHz performance with today´s technology.
Keywords :
CMOS digital integrated circuits; cache storage; delays; integrated circuit design; microprocessor chips; timing; 1 Mbit; 500 MHz; CMOS processors; differential dynamic implementation; multi-level bit line sensing scheme; on-chip cache design; overall delay; process technology; sensing delay; split read BLs; timing components; write BLs; Delay; Timing;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507742
