An 11-stage ring oscillator with nonlinear negative feedback for high speed digital applications

This paper presents the performance of an 11-stage ring oscillator for high speed digital circuits using a gate configuration with nonlinear negative feedback (NNFB). An additional transistor is introduced into the switching path of buffered FET logic (BFL) gate to reduce the logic HIGH level, thus limiting the logic swing. As the result, the switching speed of the circuits is improved by about 50% compared to conventional BFL gates, while maintaining almost the same power consumption. The performance of this logic design approach is demonstrated by an e-beam written 11-stage ring-oscillator using InP-based depletion-type heterostructure field effect transistors (DHFET). The oscillation frequency is 3.36 GHz corresponding to a delay time of 13.5 ps per gate