Improving the performance of multiprocessor systems-a study of the WorldSpan PAD

We describe a study conducted for the packet assembler/disassembler (PAD) in the WorldSpan protocol conversion service provided by AT&T. The PAD consists of several general processors, memory system, and a communications system. The protocol conversion is carried out by three processes within the PAD. A simulation model was developed as an aid for the optimal configuration and performance estimation of the PAD. The model includes the polling of the multi-drop lines, message handling among the processes, multi-processor process scheduling, and outbound link delay. The PAD performance is evaluated in terms of end-to-end delay, the delay components corresponding to different stages in the system processor usage, context switching and so on, Our study provides insights into the impact of some changes in the configuration or parameters on the PAD, as well as the performance tuning of a general multi-processor system