A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch

Author

Mu, A. ; Chia, B. ; Kondapalli, S. ; Koo, C. ; Larson, J. ; Luong Nguyen ; Sastry, R. ; Satsukawa, Y. ; Hsi-Ching Shih ; Wicki, T. ; Wu, C. ; Kenan Yu ; Xiaoyang Zhang

Author_Institution

HAL Comput. Syst., Cambell, CA, USA

fYear

1996

fDate

13-15 June 1996

Firstpage

136

Lastpage

137

Abstract

The HAL router chip is a 285 MHz 6-port plesiochronous packet-switched routing chip with non-blocking cross-bar switch. It combines very high bandwidth (4.5 GByte/s per port, 27 GByte/s total raw bandwidth), low fall-through latency (32 ns), no internal blocking, three arbitration priorities with in-order delivery, a flexible source routing scheme, virtual-cut-through routing, and robust reverse flow control.

Keywords

CMOS digital integrated circuits; electronic switching systems; field effect transistor switches; packet switching; synchronisation; telecommunication network routing; 285 MHz; 32 ns; 6-port packet-switched routing chip; HAL router chip; arbitration priorities; flexible source routing scheme; high bandwidth; in-order delivery; nonblocking cross-bar switch; plesiochronous router chip; robust reverse flow control; virtual-cut-through routing; Bandwidth; Delay; Packet switching; Robust control; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507744

Filename

507744