Title :
An energy-efficient single-chip FFT processor
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
A 1024-point single-chip Fast Fourier Transform (FFT) processor that employs algorithm, architecture, and circuit techniques to achieve an energy efficiency over 60x greater than the best known published processor, is presented. It is designed to operate at supply voltages less than 400 mV in a low threshold-voltage CMOS technology, and uses a unique "data-caching" memory architecture and "hierarchical bitline" memories to reduce power.
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; mathematics computing; memory architecture; pipeline processing; 1024-point type; 400 mV; DSP chip; data-caching memory architecture; energy-efficient processor; fast Fourier transform processor; hierarchical bitline memories; low threshold-voltage CMOS technology; single-chip FFT processor; CMOS technology; Circuits; Energy efficiency; Fast Fourier transforms; Memory architecture; Threshold voltage;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507756
