A 120 mm/sup 2/ 64 Mb NAND flash memory achieving 180 ns/byte effective program speed

Author

Jin-Ki Kim ; Koji Sakui ; Sung-Soo Lee ; Itoh, J. ; Suk-Chon Kwon ; Kanazawa, K. ; Ji-Jun Lee ; Nakamura, H. ; Kang-Young Kim ; Himeno, T. ; Jang-Rae Kim ; Kanda, K. ; Tae-Sung Jung ; Oshima, Y. ; Kang-Deog Suh ; Hashimoto, K. ; Sung-Tae Ahn ; Miyamoto, J

Author_Institution

Memory Div., Samsung Electron. Co. Ltd., Kiheung, South Korea

fYear

1996

fDate

13-15 June 1996

Firstpage

168

Lastpage

169

Abstract

Rapidly increasing solid-state mass-storage application areas are requiring low cost, high density flash memories with higher read and program throughputs. This paper describes a 3.3 V-only 64 Mb NAND flash memory fabricated using a 0.4 /spl mu/m single-metal CMOS technology. The read throughput of 40 MB/s is achieved by improving the random access time and by introducing a full-chip burst read. A typical program throughput of 5 MB/s corresponding to 180 ns/byte is achieved by using a narrow incremental step pulse programming (NISPP) technique. A staggered row decoder scheme relaxes layout limitations and improves the random access time.

Keywords

CMOS memory circuits; EPROM; NAND circuits; memory architecture; 0.4 micron; 3.3 V; 40 MB/s; 5 MB/s; 64 Mbit; NAND flash memory; NISPP scheme; chip architecture; full-chip burst read; high density flash memories; narrow incremental step pulse programming; random access time; single-metal CMOS technology; staggered row decoder scheme; CMOS technology; Costs; Decoding; Flash memory; Solid state circuits; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507757

Filename

507757